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 Null Modem Specifications
A Synchronous NULL Modem connects two synchronous serial ports without using a modem or CSU/DSU. The NULL modem wiring depends on the serial interface configuration of the SyncLink adapter: RS-232, V.35, or RS-530.
The following NULL modem cabling requirements are necessary for use with the SyncLink adapter:
Data Clocks
A synchronous NULL modem is different from the asynchronous NULL modem used with standard PC serial (COM) ports. Synchronous communication uses clock signals, which MUST be supplied to both adapters. Usually a modem or CSU/DSU provides the data clocks. When using a NULL modem, one of the adapters must provide data clocks. The SyncLink adapter can generate a clock on the AUX Clock pin of the serial interface. The clock speed is controlled by the adapter software. The NULL modem connects this clock output to the transmit and receive clock inputs on both adapters. The NULL modem must be attached with the Clock Source end to the adapter that is supplying the clock signal.
WARNING
The NULL modem wiring below connects one clock output to 4 clock inputs. Normally an output should only drive a single input. Driving multiple inputs reduces the signal strength, and may result in unreliable clock signals. If using a custom HDLC API application, connect the AUXCLK output of the adapter providing the clock only to the RxC and TxC of the remote end, and NOT the RxC and TxC of the clock source end. This reduces the load to two inputs. For this to work, the application must be able to configure the clock provider to provide the local transmit and receive clocks internally from the BRG. If this is not possible, then minimize the cable lengths to reduce the load.
It may be necessary to operate at a lower data rate than is supported with normal connections.
It may be necessary to buy an active (powered) NULL modem from a third party which uses multiple drivers to replicate a clock source for distribution to multiple clock inputs.
If connecting two multiport adapters, try placing a 6 foot cable between the adapter providing clocks and the NULL modem. This may reduce noise introduced if the null modem is too close to the clock source port.
DCD (Carrier Detect)
In the tables below, the DCD signal is driven by the DTR signal on the opposite end. In this case, DCD operates as a connection indicator that signals the remote ends readiness. An alternate method of wiring is to drive DCD from the RTS of the opposite side. In this case DCD signals that the remote is transmitting data. The choice of these two setups is application dependant.
In the tables below, each column represents the DB-25 connector pins on one end of the connection. Each row represents connections (wires) between the adapters. All pins listed in a row are connected to each other.
For example:
In the first row of the RS-232 table, the DSR and DCD signals on the clock source end are tied together AND they are connected to the DTR signal on the remote end.
|
| Clock Source End |
|
| DSR, DCD (Pins 6,8) |
DTR (Pin 20) |
| |
RTS, CTS (Pins 4,5) |
| DTR (Pin 20) |
DSR, DCD (Pins 6,8) |
| RTS, CTS (Pins 4,5) |
|
| TxC, RxC, AUXClk (Pins 15,17,24) |
TxC,RxC (Pins 15,17) |
| TxD (Pin 2) |
RxD (Pin 3) |
| RxD (Pin 3) |
TxD (Pin 2) |
| Signal Ground (Pin 7) |
Signal Ground (Pin 7) |
V.35 Null Modem (GT family/PCMCIA) |
| Clock Source End |
|
| DSR, DCD (Pins 6,8) |
DTR (Pin 20) |
| |
RTS, CTS (Pins 4,5) |
| DTR (Pin 20) |
DSR, DCD (Pins 6,8) |
| RTS, CTS (Pins 4,5) |
|
| TxC+, RxC+, AUXClk+ (Pins 15,17,24) |
TxC+,RxC+ (Pins 15,17) |
| TxC-, RxC-, AUXClk- (Pins 12,9,11) |
TxC-,RxC- (Pin 12,9) |
| TxD+ (Pin 2) |
RxD+ (Pin 3) |
| TxD- (Pin 14) |
RxD- (Pin 16) |
| RxD+ (Pin 3) |
TxD+ (Pin 2) |
| RxD- (Pin 16) |
TxD- (Pin 14) |
| Signal Ground (Pin 7) |
Signal Ground (Pin 7) |
V.35 Null Modem (legacy/obsolete) |
| Clock Source End |
|
| DSR, DCD (Pins 6,8) |
DTR (Pin 20) |
| |
RTS, CTS (Pins 4,5) |
| DTR (Pin 20) |
DSR, DCD (Pins 6,8) |
| RTS, CTS (Pins 4,5) |
|
| TxC+, RxC+, AUXClk+ (Pins 15,17,24) |
TxC+,RxC+ (Pins 15,17) |
| TxC-, RxC-, AUXClk- (Pins 13,19,23) |
TxC-,RxC- (Pin 13,19) |
| TxD+ (Pin 2) |
RxD+ (Pin 3) |
| TxD- (Pin 14) |
RxD- (Pin 16) |
| RxD+ (Pin 3) |
TxD+ (Pin 2) |
| RxD- (Pin 16) |
TxD- (Pin 14) |
| Signal Ground (Pin 7) |
Signal Ground (Pin 7) |
|
| Clock Source End |
|
| DSR+, DCD+ (Pins 6,8) |
DTR+ (Pin 20) |
| DSR-, DCD- (Pins 22,10) |
DTR- (Pin 23) |
| |
RTS+, CTS+ (Pins 4,5) |
| |
RTS-, CTS- (Pins 19,13) |
| DTR+ (Pin 20) |
DSR+, DCD+ (Pins 6,8) |
| DTR- (Pin 23) |
DSR-, DCD- (Pins 22,10) |
| RTS+, CTS+ (Pins 4,5) |
|
| RTS-, CTS- (Pins 19,13) |
|
| TxC+, RxC+, AUXClk+ (Pins 15,17,24) |
TxC+,RxC+ (Pins 15,17) |
| TxC-, RxC-, AUXClk- (Pins 12,9,11) |
TxC-,RxC- (Pins 12,9) |
| TxD+ (Pin 2) |
RxD+ (Pin 3) |
| TxD- (Pin 14) |
RxD- (Pin 16) |
| RxD+ (Pin 3) |
TxD+ (Pin 2) |
| RxD- (Pin 16) |
TxD- (Pin 14) |
| Signal Ground (Pin 7) |
Signal Ground (Pin 7) |
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